Low temperature MIM capacitor for mixed-signal/RF applications

ABSTRACT

A method for fabricating an MIM capacitor on a substrate. A region of the substrate is dedicated for use as an electrode area of the MIM capacitor. The electrode area of the MIM capacitor may be increased by utilizing at least one spacer formed on an associated planar metal surface, wherein the planar metal surface is formed upon the substrate. An increase in a gain factor of the electrode area is thus dependent upon an associated spacer height and particular number of islands or vias. A roughened surface is thus created for use as a roughened electrode for subsequent capacitor processes. Fabricating spacers made of conducting or non-conducting materials on the associated planar metal surface can create such an electrode. The MIM capacitor formed thereof can be utilized in mixed-signal and RF applications and is fully compatible with COMS logic fabrication processes.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor devices andfabrication methods thereof. More specifically, the present inventionrelates to a semiconductor device having a capacitor and a contact plugin a DRAM (Dynamic Random Access Memory) or the like, and to amanufacturing method thereof. The present invention also relates to MIMcapacitor fabrication methods and systems. The present invention alsorelates to logic-based embedded DRAM devices and manufacturing methodsthereof.

BACKGROUND OF THE INVENTION

[0002] In the integrated circuit (IC) industry, manufacturers arecurrently embedding dynamic random access memory (DRAM) arrays on thesame substrate as CPU cores or other logic devices. This technology isbeing referred to as embedded DRAM (eDRAM). Embedded DRAM generally canprovide micro-controller (MCU) and other embedded controllers fasteraccess to larger capacities of on-chip memory at a lower cost than thatcurrently available using conventional embedded static random accessmemory (SRAM) and/or electrically erasable programmable read only memory(EEPROM).

[0003] A semiconductor memory cell, such as a cell for DRAM or embeddedDRAM, is mainly composed of transistors and capacitors. Therefore,improvement in the efficiency of such structures tends to lead thedirection in which the technology is developing. DRAM is a volatilememory, and the manner in which to store digital signals is generallydetermined by the charge or discharge of the capacitor in the DRAM. Whenthe power applied to the DRAM is turned off, the data stored in thememory cell completely disappears.

[0004] A typical DRAM cell usually includes at least one field effecttransistor (FET) and at least one capacitor. The capacitor is used tostore the charge (i.e., signals) in the cell of DRAM. If more chargescan be stored in the capacitor, the capacitor has less interference whenthe amplifier senses the data. In recent years, DRAM memory cells havebeen aggressively miniaturized from generation to generation. Even ifthe memory cell is minimized, a constant capacitance in the range of 20fF to 30 fF is needed in the storage capacitor of the cell to store theinformation.

[0005] When the semiconductor enters the deep sub-micron process, thesize of the device becomes smaller. For the conventional DRAM structure,this means that the space used by the capacitor becomes smaller. Sincecomputer software is gradually becoming huge, even more memory capacityis required. In the case where it is necessary to have a smaller size ofeach memory cell with an increased capacity of memory, the conventionalmethod of fabricating the DRAM capacitor must change in order to fulfillthe requirements of the trend.

[0006] There are two approaches at present for reducing the size of thecapacitor (i.e., reducing its footprint, while increasing its memorycapacity). One approach involves the selection of a high-dielectricmaterial. The other approach involves increasing the surface area of thecapacitor electrodes by utilizing 3-dimensional or vertical structures.

[0007] There are two main types of vertical capacitor structures forDRAM. The first type of vertical structure is the deep trench-type,which can be formed by digging out a trench and forming capacitors forelectrodes and dielectrics inside the trench. The second type ofvertical structure is the stacked-type, which can be formed bydepositing a capacitive dielectric layer and a conductive layer insequence for the capacitor.

[0008] When a dielectric material with a relatively high dielectricconstant is used in a stacked or trench capacitor, the materials formanufacturing the upper and the bottom electrodes need to be carefullyselected in order to enhance the performance of the capacitor (e.g.,reducing leakage current, or suppressing interfacial oxide formation,etc.). A structure known as a metal-insulator-metal (MIM) structurepossesses a low-interfacial reaction specificity to enhance theperformance of the capacitor. Therefore, it has become an importanttopic of research for the semiconductor capacitor in the future.

[0009] The obtainable capacitance of each cell's storage capacitor tendsto decrease due to the level of the miniaturization of the storage cell.On the other hand, the necessary capacitance of the capacitor is almostconstant when the storing voltage to be applied across the capacitor isfixed. Therefore, it is necessary for the capacitor to compensate thecapacitance decrease due to the miniaturization by, for example,increasing the surface area of the capacitor. This surface area increasehas been popularly realized by increasing the roughness of the lowerelectrode (e.g., or, storage electrode) surface of the capacitor.

[0010] In addition to the application of capacitors to DRAM cells, acapacitor is generally one of the most useful of passive components thatis commonly integrated with active bipolar or CMOS transistors in modernVLSI devices. Integrated capacitors are commonly fabricated betweenpolysilicon (i.e. PIP capacitors), poly to polycide/metal (i.e. MIScapacitors), or metal-to-metal (i.e. MIM) capacitors. All of these typesof capacitors may be planar in nature for process compatibility andsimplicity and can also be formed as 3-dimensional structures forreducing footprints.

[0011] The MIM capacitor provides superior advantages formixed-signal/RF applications than other PIP or MIS capacitors. An MIMcapacitor is typically fabricated in the BEOL (back-end-of-line) andrequires low process temperatures (i.e., less than 450 C.). Therefore, aminimum disturbance of transistor parameters is present. Additionally,MIM capacitors offer excellent linearity and symmetry due to the lack ofthe so-called depletion effect in the polysilicon layer, which isgenerally evidenced in PIP or MIS capacitors. MIM capacitors thus arefully compatible with logic processes in BEOL and are preferred formodern mixed-signal or RF applications. Typical MIM capacitors have adielectric of PE-oxide (e.g., 400A) deposited at a temperature of 450ECor less with a capacitance density of approximately 1 fF/um² in planarstructures.

[0012] For increasingly complex mixed-signal and RF applications, theplanar MIM capacitor area is limited by chip size parameters. Thus, thepresent inventors recognize that a need exists to fabricate capacitorshaving a small footprint (i.e., higher capacitance density). One commontechnique for raising the capacitance density involves reducing thedielectric thickness at the cost of worsening linearity and promotinghigher leakage currents resulting from higher operating fields. Anothercommon technique involves the utilization of high-k materials (e.g.,Ta₂O₅). Implementing such a technique, however, often requires specialstructures of electrode materials that raise complex process integrationissues. Still another common technique of increasing capacitance densityinvolves increasing the effective electrode area by roughening theelectrode surface.

[0013] Based on the foregoing, the present inventors have concluded thatnew techniques are needed for increasing capacitance density. Thepresent inventors thus present new techniques and devices thereof forincreasing the electrode area of MIM capacitors utilizing spacerformations on planar metal surfaces. Such new fabrication methods arefully compatible with CMOS technology and represent a promising futurefor system-on-chip (SOC) with signal-mix and RF applications.

BRIEF SUMMARY OF THE INVENTION

[0014] The following summary of the invention is provided to facilitatean understanding of some of the innovative features unique to thepresent invention, and is not intended to be a full description. A fullappreciation of the various aspects of the invention can be gained bytaking the entire specification, claims, drawings, and abstract as awhole.

[0015] It is therefore one aspect of the present invention to provide animproved semiconductor fabrication method and devices thereof.

[0016] It is another aspect of the present invention to provide a methodfor fabricating a MIM capacitor.

[0017] It is yet another aspect of the present invention to provide amethod and for fabricating an MIM (metal insulator metal) capacitorutilized in an embedded DRAM-based semiconductor device.

[0018] It is still a further aspect of the present invention to providea method for fabricating a low-temperature MIM capacitor formixed-signal/RF applications.

[0019] The above and other aspects of the present invention can thus beachieved as is now described. A method for fabricating an MIM capacitoron a substrate is disclosed herein. A region of the substrate isgenerally dedicated for use as an electrode area of the MIM capacitor.The electrode area of the MIM capacitor may be increased utilizing atleast one spacer formed on an associated planar metal surface, whereinthe planar metal surface is generally formed upon the substrate. Anincrease in a gain factor of the electrode area is thus dependent uponan associated spacer height and particular islands or vias. A roughenedsurface is thus created for use as a roughened electrode for subsequentcapacitor processes. Fabricating spacers made of conducting ornon-conducting materials on the associated planar metal surface cancreate such an electrode. The MIM capacitor formed thereof can beutilized in mixed-signal and RF applications and is fully compatiblewith COMS logic fabrication processes.

[0020] Thus, two novel fabrications methods for forming low-temperaturesMIM capacitors with surface roughening are described herein. The firstMIM capacitor formation technique disclosed herein, in accordance with apreferred embodiment of the present invention, involves the formation ofPE-oxide islands on a metal surface. The PE-oxide islands (i.e., oxideislands) will be removed later and is therefore comprise disposablePE-oxide islands. Spacers of conducting materials (e.g., TiN or TaN) areformed by deposition and etching back techniques about the oxideislands. Such a conducting spacer thus provides a short to the metalsurface below. Thereafter, the oxide islands are removed. The metalsurface with conducting spacers thus becomes a roughened electrode forsubsequent capacitor processes of dielectric deposition and topelectrode formation.

[0021] The second MIM capacitor formation technique disclosed herein, inaccordance with an alternative embodiment of the present invention,involves the formation of vias in the oxide layer on metal. After thevias are filled through spin coating with protection material (e.g.,photo-resist, organic ARC, and so forth), then the protection materialin-between vias is removed by performing CMP (Chemical MechanicalPolishing) or an etch back operation. Now, the oxide surface is thenexposed and the inside of the via is filled with a protecting material.An anisotropic oxide etch can then be performed, which leads to theformation of oxide spacers around the protection material (e.g.,photoresist organic ARC) in the vias. Following PR removal and cleaning,the oxide spacers around the prior vias on the metal surface are coatedwith a thin conduction material (e.g., TiN or TaN) to form a roughenedelectrode surface. Subsequent capacitor processes may then follow tocomplete remaining fabrication steps. The area gain factor of theresulting electrode thus depends on the spacer height and dimensions ofthe formed islands (i.e., for the 1^(st) technique) or vias (i.e., forthe 2^(nd) technique).

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying figures, in which like reference numerals referto identical or functionally-similar elements throughout the separateviews and which are incorporated in and form part of the specification,further illustrate the present invention and, together with the detaileddescription of the invention, serve to explain the principles of thepresent invention.

[0023]FIG. 1 depicts a first step of a prior art fabrication process inwhich surface roughing techniques are not utilized;

[0024]FIG. 2 illustrates a second step of a prior art fabricationprocess in which surface roughing techniques are not utilized;

[0025]FIG. 3 depicts a third step of a prior art fabrication process inwhich surface roughing techniques are not utilized;

[0026]FIG. 4 illustrates a fourth step of a prior art fabricationprocess in which surface roughing techniques are not utilized;

[0027]FIG. 5 depicts a fifth step of a prior art fabrication process inwhich surface roughing techniques are not utilized;

[0028]FIG. 6 illustrates a sixth step of a prior art fabrication processin which surface roughing techniques are not utilized;

[0029]FIG. 7 depicts a seventh step of a prior art fabrication processin which surface roughing techniques are not utilized;

[0030]FIG. 8 illustrates an eighth step of a prior art fabricationprocess in which surface roughing techniques are not utilized;

[0031]FIG. 9 depicts a ninth step of a prior art fabrication process inwhich surface roughing techniques are not utilized;

[0032]FIG. 10 illustrates a first step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0033]FIG. 11 depicts a second step of a fabrication process for forminga roughened surface around disposable oxide islands, in accordance witha preferred embodiment of the present invention;

[0034]FIG. 12 illustrates a third step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0035]FIG. 13 depicts a fourth step of a fabrication process for forminga roughened surface around disposable oxide islands, in accordance witha preferred embodiment of the present invention;

[0036]FIG. 14 illustrates a fifth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0037]FIG. 15 depicts a sixth step of a fabrication process for forminga roughened surface around disposable oxide islands, in accordance witha preferred embodiment of the present invention;

[0038]FIG. 16 illustrates a seventh step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0039]FIG. 17 depicts an eighth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0040]FIG. 18 illustrates a ninth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0041]FIG. 19 depicts a tenth step of a fabrication process for forminga roughened surface around disposable oxide islands, in accordance witha preferred embodiment of the present invention;

[0042]FIG. 20 illustrates an eleventh step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0043]FIG. 21 depicts a twelfth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0044]FIG. 22 illustrates a thirteenth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention;

[0045]FIG. 23 depicts a fourteenth step of a fabrication process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention FIG. 24illustrates a first step of a fabrication process in which a surface isroughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0046]FIG. 25 depicts a second step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0047]FIG. 26 illustrates a third step of a fabrication process in whicha surface is roughened by oxide spacers around vias, in accordance withan alternative embodiment of the present invention;

[0048]FIG. 27 depicts a fourth step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0049]FIG. 28 illustrates a fifth step of a fabrication process in whicha surface is roughened by oxide spacers around vias, in accordance withan alternative embodiment of the present invention;

[0050]FIG. 29 depicts a sixth step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0051]FIG. 30 illustrates a seventh step of a fabrication process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention;

[0052]FIG. 31 depicts an eighth step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0053]FIG. 32 illustrates a ninth step of a fabrication process in whicha surface is roughened by oxide spacers around vias, in accordance withan alternative embodiment of the present invention;

[0054]FIG. 33 depicts a tenth step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0055]FIG. 34 illustrates an eleventh step of a fabrication process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention;

[0056]FIG. 35 depicts a twelfth step of a fabrication process in which asurface is roughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention;

[0057]FIG. 36 illustrates a thirteenth step of a fabrication process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention;

[0058]FIG. 37 depicts a fourteenth step of a fabrication process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention;

[0059]FIG. 38 illustrates a capacitor area configuration, in accordancewith a preferred or alternative embodiment of the present invention;

[0060]FIG. 39 depicts a first step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0061]FIG. 40 illustrates a second step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0062]FIG. 41 depicts a third step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0063]FIG. 42 illustrates a fourth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0064]FIG. 43 depicts a fifth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0065]FIG. 44 illustrates a sixth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0066]FIG. 45 depicts a seventh step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0067]FIG. 46 illustrates an eighth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0068]FIG. 47 depicts a ninth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0069]FIG. 48 illustrates a tenth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0070]FIG. 49 depicts an eleventh step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0071]FIG. 50 illustrates a twelfth step of a fabrication process inaccordance with an alternative embodiment of the present invention;

[0072]FIG. 51 depicts a thirteenth step of a fabrication process inaccordance with an alternative embodiment of the present invention; and

[0073]FIG. 52 illustrates a sixteenth step of a fabrication process inaccordance with an alternative embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0074] The particular values and configurations discussed in thesenon-limiting examples can be varied and are cited merely to illustrateembodiments of the present invention and are not intended to limit thescope of the invention.

[0075] In order to understand the semiconductor fabrication techniquesdisclosed herein, in accordance with preferred or alternativeembodiments of the present inventions, it is helpful to understand priorart semiconductor fabrication techniques in greater detail. The priorart fabrication technique illustrated in FIGS. 1 to 9 is presented forillustrative and edification purposes only and is not a limiting featureof the present invention. FIGS. 1 to 9 represent one example of processflow for conventional planar MIM capacitors for mixed-signal/RFapplications. The MIM capacitor in FIGS. 1 to 9 have an area of 25 m×25m and approximately 1 fF/um² in a planar AL/PE-oxide/Al structure.

[0076]FIG. 1 thus depicts a first step 10 of a prior art fabricationprocess in which surface roughing techniques are not utilized. Asillustrated in FIG. 1, a layer 14 of TiN (e.g., 250 A) can be depositedabove substrate 12. Layer 16, deposited above layer 14, comprises Al—Cu(i.e., aluminum with approximately 1-2% copper, 4 kA). Finally, a layer18 of TiN (e.g., 250 A) is deposited above layer 16. Layers 14 and 18are commonly referred to as capping layer for Al—Cu layer 16. Layers 14,16 and 18 together thus may comprise a complete conducting layer ininterconnection. Such a complete interconnect conducting layer may berepeated for multi-layer connection in modern BEOL technology of CMOS,i.e. six layers for a typical 0.13 Fm CMOS technology. As illustrated inFIG. 1, the label “metal-5” denotes the 5^(th) conducting layer, and canserve as the bottom electrode of the MIM capacitor. Note that in FIGS.1-9 herein, like parts are indicated by identical reference numerals.

[0077]FIG. 2 illustrates a second step 20 of a prior art fabricationprocess in which surface roughing techniques are not utilized. Asillustrated in FIG. 2, a layer 22 is deposited above layer 18. Layer 22generally comprises a PE-oxide (i.e. approximately 400 A) withdeposition at a low temperature of approximately 400 EC.

[0078]FIG. 3 depicts a third step 30 of a prior art fabrication processin which surface roughing techniques are not utilized. As indicated inFIG. 3, a layer 23 of TiN (e.g., 250 A) can be deposited above layer 22.A layer 24 can thereafter be deposed above layer 23. Layer 24 can becomposed of, for example, Al—Cu (1.2 kA). Finally, a layer 26 of TiN(e.g., 750 A) may be deposited above layer 24 as a capping layer. Layers23, 24 and 26 in FIG. 3 are referred to as capacitor top metal (CTM)layers, including TiN (250 A), Al—Cu (1200 A) and Tin (750 A).

[0079]FIG. 4 illustrates a fourth step 40 of a prior art fabricationprocess in which surface roughing techniques are not utilized. Asdepicted in FIG. 4, a photo-resist 34 is formed above layer 28. Layer 28is an SION layer having a value of approximately 300 A and serving as ananti-reflective coating (ARC) layer at the bottom of the photoresistlayer 34. Thus, layer 28 is referred to as the bottom anti-reflectivecoating (BARC) in FIG. 4. Photoresist 34 is then patterned for acapacitor top metal (CTM).

[0080]FIG. 5 depicts a fifth step 50 of a prior art fabrication processin which surface roughing techniques are not utilized. As illustrated inFIG. 5, after etching layer 28, 26, 24 and 23, and removing photo-resist34 to form a structure 52 of capacitor top metal (CTM) is achieved. TheCTM structure 52 surface area is approximately 25 um×25 um. FIG. 6illustrates a sixth step 60 of a prior art fabrication process in whichsurface roughing techniques are not utilized. As depicted in FIG. 6, alayer 54 of SiON (e.g., 300 A) is deposited. Note that layer 54 andlayer 28 are both SiON in structure 52.

[0081]FIG. 7 depicts a seventh step 70 of a prior art fabricationprocess in which surface roughing techniques are not utilized. FIG. 7illustrates an FSG deposition operation followed by CMP planarization.Then, Via-5 photo patterning occurs followed by a via-5 etching step.Note that the term FSG refers to fluorinated silicon oxide. Note thatVia-5 etching can utilize SiON as an etch stop and then reach themetal-5 and CTM illustrated in FIG. 7. FIG. 8 illustrates an eighth step80 of a prior art fabrication process in which surface roughingtechniques are not utilized. As indicated in FIG. 8, the vias are filledwith Tungsten (W) by well-known W-deposition and followed by CMP or etchback methods. FIG. 9 depicts a ninth step 90 of a prior art fabricationprocess in which surface roughing techniques are not utilized. Finally,as indicated in FIG. 9, metal-6 layers (i.e. Al, with TiN cappinglayers) may be formed and patterned above the W-plugs in vias, therebyforming an MIM capacitor. Thus, those skilled in the art can appreciatethat the MIM structure formed as a result of the fabrication processingoperations illustrated in FIGS. 1-9 contains a capacitor that is limitedby the CTM area and PE-oxide thickness of layer 22.

[0082] FIGS. 10-21 illustrate one MIM capacitor fabrication that may beimplemented in accordance with a preferred embodiment of the presentinvention. FIGS. 10-21 depicts a method for forming an MIM capacitorhaving a roughened electrode surface. Note that in FIGS. 10-21 herein,like parts are indicated by identical reference numerals. FIG. 10illustrates a first step 110 of a MIM capacitor process for forming aroughened surface around disposable oxide islands, in accordance with apreferred embodiment of the present invention. As indicated in FIG. 10,a layer 142 is formed above a substrate 140. Substrate 140 representsthe surface after all front-end-of-line (FEOL) and BEOL fabricationoperation before layer 142 deposition. Layer 142 may be composed of TiN(250 A). A layer 144 is then formed above layer 142. Layer 144 may becomposed of Al—Cu (4 kA).

[0083]FIG. 11 depicts a second step 111 of a MIM capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Asindicated in FIG. 11, a layer 146 of PE-oxide (1 kA B 15 kA) isdeposited above layer 144 at a low temperature of approximately 400 EC.

[0084]FIG. 12 illustrates a third step 112 of a MIM capacitor processfor forming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Asdepicted in FIG. 12, after PE-oxide photo patterning and etchingoperations are processed. PE-oxide islands 150, 152, 154 thus are formedbelow photo-resists 160, 158, and 156. Photoresist is then removed.

[0085]FIG. 13 depicts a fourth step 113 of a MIM capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention.Following island topography, as illustrated in FIG. 12, a thin TiN layer162 is deposited, as depicted in FIG. 13. The thin conducting layer 162of TiN (i.e. approximately 250 A) is in direct contact to layer 144 aswell as PE-oxide islands.

[0086]FIG. 14 illustrates a fifth step 114 of a MIM capacitor processfor forming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Asdepicted in FIG. 14, a direct TiN etch back is performed to form TiNspacers 182, 180, 178, 174, 172, and 170 around the oxide islands (i.e.ring shaped). For example, spacers 180 and 182 are actually can form aring around the oxide island 150. The oxide islands 150, 152, and 154are removed and the TiN spacers remain standing on the Al—Cu surface(i.e., layer 144). Note that the TiN spacers are configured to form anelectrical short to the metal surface (i.e., layer 144) below. Asindicated in FIG. 14, TiN spacers 182, 180, 178, 174, 172, and 170 canbe formed by anisotropic TiN etch back operations, followed by PE-oxideremoval. The oxide islands are therefore referred to as disposable oxideislands.

[0087]FIG. 15 depicts a sixth step 115 of a MIM capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Afterthe TiN spacer formation, an optional thin TiN glue/barrier layer 190 ofapproximately 250 A can be deposited to firmly secure and smooth sharptips of TiN spacers on the metal surface as the bottom electrode. Notethat the overall TiN/Al—Cu/Tin spacer is labeled as Ametal-5@ (byassuming prior metal-1 to metal-4 layers as well as intermetaldielectric layers are processed by conventional CMOS fabricationprocesses and are included in the substrate 140).

[0088]FIG. 16 illustrates a seventh step 116 of a MIM capacitor processfor forming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. After ametal-5 (i.e., bottom electrode) is formed, a thin dielectric layer 192(e.g., PE-oxide of approximately 400 A) can be deposited at 400 EC.

[0089]FIG. 17 depicts an eighth step 111 of a MIM capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention.Following processing of the operation illustrated at block 17, asequential deposition of TiN (200A) layer 193, Al—Cu (1.2 kA) layer 194,and TiN (700 A) layer 196 can be performed to form an MIM capacitor topelectrode (referred to as CTM structure 200 in FIG. 18. It isunderstood, of course, that the values assigned to the various layersdescribed herein are presented for illustrative purposes only and arenot considered limiting features of the present invention.

[0090]FIG. 18 illustrates a ninth step 200 of a MIM capacitor processfor forming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. A SiONBARC deposition of approximately 320 A is performed along with acapacitor top metal (CTM) photo patterning operation. As indicated inFIG. 18, photoresist pattern 200 for CTM is formed above layer 196.

[0091]FIG. 19 depicts a tenth step 119 of a MIM Capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Asindicated in FIG. 19, a capacitor top metal (CTM) etching operation isperformed with a stop on PE oxide (i.e., CTM surface area can beapproximately 25 Fm×25 Fm). After removing the photoresist, the CTM isformed.

[0092]FIG. 20 illustrates an eleventh step 120 of a MIM capacitorprocess for forming a roughened surface around disposable oxide islands,in accordance with a preferred embodiment of the present invention.Thus, after forming the CTM structure, another SION layer (300 A) isdeposited for sealing the edge of dielectric CTM.

[0093]FIG. 21 depicts a twelfth step 121 of a MIM capacitor process forforming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. In FIG.21, an FSG deposition operation of approximately 10 kA-20 kA isperformed and followed by CMP planarization for aninter-metal-dielectric (IMD-5) layer. See reference numeral 197 for anindication of the FSG deposition operation. Then Via-5 is formed byphoto patterning, oxide etching and photoresist removing.

[0094]FIG. 22 illustrates a thirteenth step 121 of a MIM capacitorprocess for forming a roughened surface around disposable oxide islands,in accordance with a preferred embodiment of the present invention. Asindicated in FIG. 22, Ti/TiN/W depositions for Via-5 filling operationsare performed, followed by CMP for isolation of vias.

[0095]FIG. 23 depicts a thirteenth step 123 of a MIM capacitor processfor forming a roughened surface around disposable oxide islands, inaccordance with a preferred embodiment of the present invention. Asillustrated in FIG. 23, metal-6 (including TiN/Cu—Al/Tin) depositionsare performed followed by photo patterning and etching. Remainingfabrication processes can be implemented for mixed-signal/RF devices.

[0096] FIGS. 24-37 illustrate an alternative embodiment of the presentinvention in which a surface may be roughened by one or more oxidespacers formed around vias. Note that in FIGS. 24 to 37, like parts areindicated by identical reference numerals. FIG. 24 thus illustrates afirst step 124 of a MIM capacitor process in which a surface isroughened by oxide spacers around vias, in accordance with analternative embodiment of the present invention. As indicated in FIG.24, a substrate 300 is utilized (with all prior FEOL and BEOLfabrication operations completed) upon which subsequent layers for MIMcapacitor may be formed. A layer 302 is composed of TiN (250A) can bedeposited above substrate 300. A layer 304, is Al—Cu (4 kA), isdeposited above layer 302. Thus, FIG. 24 describes an operational stepin which metal layers is deposited to form a bottom electrode.

[0097]FIG. 25 depicts a second step 125 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As illustratedin FIG. 25, a PE-oxide, layer 306, deposition step is performed at a lowtemperature of approximately 400 EC. Layer 306 is formed above layer304.

[0098]FIG. 26 illustrates a third step 126 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As indicated inFIG. 26, tapered via holes are formed (instead of oxide islands, whichis the case with the configuration of the preferred embodiment of thepresent invention described herein with respect to FIG. 12). Thus, aPE-oxide photo patterning and etching operations are performed to formone or more tapered vias, followed by photoresist removal. As indicatedin FIG. 26, vias in PE-oxide 308, 309, and 310 are formed photoresistopenings of 312, 314, and 316.

[0099]FIG. 27 depicts a fourth step 127 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As indicated inFIG. 27, photoresist (PR) spin coating and removal operations areperformed by partial photo-exposure and development or etch back or CMPuntil PE-oxide surface is exposed.

[0100]FIG. 28 illustrates a fifth step 128 of a fabrication process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. With thetapered via holes protected by PR, an anisotropic oxide etchingoperation is implemented to remove the exposed PE-oxide layers,resulting in oxide spacers (rings) around the vias, as illustrated inFIG. 28.

[0101]FIG. 29 depicts a sixth step 129 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. After PR (invias) removal, a thin TiN layer 311 of approximately 250 A can bedeposited on the oxide spacer surface to secure oxide spacer ringssmoothly and firmly standing on a metal surface. Note that in FIG. 29,reference numeral 313 generally refers to the bottom electrode (e.g. themetal-5 layer). Reference numerals 315, 317, 318, 318, 319, 321 and 323generally indicate the presence of an oxide spacer structure with ringshape (i.e. 317 and 318 are formed as a ring around via 309).

[0102]FIG. 30 illustrates a seventh step 130 of a MIM capacitor processin which a surface is roughened by oxide spacers around vias, inaccordance with an alternative embodiment of the present invention. Asdepicted in FIG. 30, capacitor dielectric film of PE-oxide layer 333,with thickness of approximately 400 A is performed at a temperature ofabout 400 EC.

[0103]FIG. 31 depicts an eighth step 131 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. FIG. 31indicates layers for capacitor top metal (CTM), including a TiN layer337 of approximately 250 A, an Al—Cu layer 339 of approximately 1200 A,and a TiN layer 341 of approximately 700 A to 750 A.

[0104]FIG. 32 illustrates a ninth step 132 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As illustratedin FIG. 32, an SiON BARC deposition 345 of approximately 320 A isperformed, followed by photoresist pattern 343 capacitor top metal (CTM)is performed.

[0105]FIG. 33 depicts a tenth step 133 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As illustratedin FIG. 33, a capacitor top metal (CTM) layer etching operation isperformed by stopping on PE-oxide. The CTM surface area is approximately25 Fm×25 Fm.

[0106]FIG. 34 illustrates an eleventh step 134 of a MIM capacitorprocess in which a surface is roughened by oxide spacers around vias, inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 34, a SiON BARC deposition 353 operation ofapproximately 300A is performed for sealing the edge of capacitordielectric around CTM.

[0107]FIG. 35 depicts a twelfth step 135 of a MIM capacitor process inwhich a surface is roughened by oxide spacers around vias, in accordancewith an alternative embodiment of the present invention. As indicated inFIG. 35, an FSG deposition (10 kA-20 kA) 363 operation is performed.Additionally, a CMP planarization operation is performed for planarizinginter-metal-dielectric (IMD-5). Via-5 photo patterning and oxide etchingis performed so that vias (via-5 ) are formed after photoresist removal.

[0108]FIG. 36 illustrates a thirteenth step 136 of a MIM capacitorprocess in which a surface is roughened by oxide spacers around vias, inaccordance with an alternative embodiment of the present invention. FIG.36 depicts Ti/TiN/W depositions for Via-5 filling, followed by CMP oftungsten for isolation. FIG. 37 depicts a fourteenth step 137 of afabrication process in which a surface is roughened by oxide spacersaround vias, in accordance with an alternative embodiment of the presentinvention. FIG. 37 illustrates metal-6 layers (TiN/Cu-Al/TiN)depositions, followed by photo patterning and etching for formation ofinterconnect.

[0109]FIG. 38 generally illustrates capacitance increases that may beobtained according to the processing steps described herein, inaccordance with preferred or embodiments of the present invention.Configuration 138 of FIG. 38 indicates a increase of electrode area canbe obtained from roughened surface (by spacers) on a foot area of 25Fm×25 Fm. Capacitance density is thus enhanced by this invention (i.e.prior art) as shown in the following estimations.

[0110] Two fabrication cases have been described herein. A first case isdescribed in accordance with a preferred embodiment of the presentinvention, while a second case is described in accordance with analternative embodiment of the present invention. In the case of thepreferred embodiment described herein, for example, if the followingholds true:

[0111] (1) PE-oxide island=1 um in diameter;

[0112] (2) PE-oxide island spacing=1u;

[0113] Then, given an island height of approximately 3 kA, the formedelectrode area of MIM capacitor is approximately 896 um², which amountsto a 43% increase in area (than the non-roughened foot area). Given anisland height of approximately 5 kA, the formed MIM capacitor area isapproximately 1077 um², which amounts to a 73% increase in areacapacitance. Given an island height of approximately 8 kA, the formedMIM capacitor area is approximately 1349 um², which amounts to a 116%increase in area capacitance. These calculations can be obtained basedon the fact that currently there are not more than 144 oxide islands oncurrent MIM capacitor planes (i.e., 25 um by 25 um).

[0114] In the case of the alternative embodiment described herein, forexample, if the following holds true:

[0115] (3) PE-oxide island=0.5 um in diameter

[0116] (4) PE-oxide island spacing=0.5 um

[0117] Then, given an island height of approximately 3 kA, the formedMIM capacitor area is approximately 1710 um², which amounts to a 174%increase in area capacitance. Given an island height of approximately 5kA, the formed MIM capacitor area is approximately 2434 um², whichamounts to a 289% increase in area capacitance. Given an island heightof approximately 8 kA, the formed MIM capacitor area is approximately3520 um², which amounts to a 463% increase in area capacitance. Thesecalculations can be obtained based on the fact that currently there arenot more than 576 oxide islands on current MIM capacitor planes.

[0118] The present invention thus discloses a method for fabricating anMIM capacitor on a substrate. A region of the substrate is generallydedicated for use as an electrode area of the MIM capacitor. Theelectrode area of the MIM capacitor may be increased by utilizing atleast one spacer formed on an associated planar metal surface, whereinthe planar metal surface is generally formed upon the substrate. Anincrease in a gain factor of the electrode area is thus dependent uponan associated spacer height and particular islands or vias. A roughenedsurface is thus created for use as a roughened electrode for subsequentcapacitor processes. Fabricating spacers made of conducting ornon-conducting materials on the associated planar metal surface cancreate such an electrode. The MIM capacitor formed thereof can beutilized in mixed-signal and RF applications and is fully compatiblewith COMS logic fabrication processes.

[0119] Thus, two novel fabrications methods for forming low-temperaturesMIM capacitors with surface roughening are described herein. The firstMIM capacitor formation technique disclosed herein, in accordance with apreferred embodiment of the present invention, involves the formation ofPE-oxide islands on a metal surface. The PE-oxide islands (i.e., oxideislands) will be removed later. Spacers of conducting materials (e.g.,TiN or Tan) are formed by deposition and etching techniques about theoxide islands. Such a conducting spacer thus provides a short to themetal surface below. Thereafter, the oxide islands are removed. Themetal surface with conducting spacers there above thus becomes aroughened electrode for subsequent capacitor processes.

[0120] The second MIM capacitor formation technique disclosed herein, inaccordance with an alternative embodiment of the present invention,involves the formation of oxide vias with tapered edge on metal. Afterthe vias are filled through spin coating and removal with protectionmaterial (e.g., photoresist, organic ARC, etc.), protection material onthe oxide surface can be removed by etch back or CMP. The oxide surfaceis then etched by an anisotropic oxide etching, so that oxide spacersaround the vias are formed. Following PR cleaning (i.e., a cleaningstep), the oxide spacers on the metal surface is coated with a thinconduction material, such as, form example, TiN or TaN, to form aroughened electrode surface. Subsequent capacitor processes may thenfollow to complete any remaining fabrication steps. The area gain factorof the resulting electrode thus depends on the spacer height anddimensions of the formed islands or vias.

[0121] The present invention thus discloses an innovative semiconductorMIM capacitor fabrication process that is fully compatible with logicprocesses for mixed-signal and/or RF applications. The present inventionalso discloses unique fabrication methods in which the effectiveelectrode surface area is significantly enlarged so that the capacitancedensity (per unit foot area) can be greatly enhanced by a factor of 2 ormore. FIG. 38 in particular illustrates the fact that capacitancedensity can be increased by a factor of 2 or more, which greatly reducesMIM capacitor footprints with the same capacitance value. The effectiveelectrode area increase thus depends on the height of spacers and thedensity of spacer formations thereof.

[0122] FIGS. 39-52 illustrate an alternative fabrication process, whichcan be implemented in accordance with an alternative embodiment of thepresent invention. In FIGS. 39-52, identical or similar parts arerepresented by identical reference numerals. FIGS. 39-52 represent asequential series of fabrication steps. FIG. 39 depicts a first step 539of a fabrication process in accordance with an alternative embodiment ofthe present invention. As indicated in FIG. 39, metal deposition for abottom electrode involves the deposition of layers 504 and 502 above asubstrate 506. Layer 504 comprises a layer of TiN (e.g., 250A) and layer502 comprises a layer of Al—Cu (e.g., 4 kA).

[0123]FIG. 40 illustrates a second step 540 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 40, a sacrificial PE-oxide layer of approximately 1 kAto 15 kA can be deposited above layer 502 at a low temperature ofapproximately 400 degrees Celsius.

[0124]FIG. 41 depicts a third step 541 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 41, a PE-oxide photo patterning and etching operationcan occur, followed thereafter by photoresist removal. In FIG. 41,photoresists 510, 512, and 514 are respectively indicate above carvedout PE-oxide islands 516, 518 and 520, which are formed from layer 508(i.e., see FIG. 40).

[0125]FIG. 42 illustrates a fourth step 542 of a fabrication process inaccordance with an alternative embodiment of the present invention. InFIG. 42, PR spin coating and removal by partial photo-exposure anddevelopment can be processed. Alternatively, an etch back or CMPoperation may be implemented until the PE-oxide surface is exposed. FIG.42 depicts a photoresist layer 522.

[0126]FIG. 43 depicts a fifth step 543 of a fabrication process inaccordance with an alternative embodiment of the present invention. FIG.43 illustrates a fabrication step in which an-isotropic RIE etching isperformed to form oxide spacers (i.e., oxide spacer rings) 524, 526,528, 530, 532 and 534. A photoresist removal step can follow.

[0127]FIG. 44 illustrates a sixth step 544 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 44, a thin TiN layer 536 (e.g., 250A) of film isdeposited above oxide spacers 524, 526, 528, 530, 532, and 534. Notethat such oxide spacers form rings. For example, oxide spacers 524 and526 form a ring, while oxide spacers 528 and 530 also form a ring.Similarly, oxide spacers 532 and 534 form a ring. Thus, according toFIG. 44, a thin TiN layer is deposited on the oxide spacers and Al—Cusurfaces (i.e., layer 502).

[0128]FIG. 45 depicts a seventh step 545 of a fabrication process inaccordance with an alternative embodiment of the present invention. FIG.45 illustrates an fabrication step in which a dielectric layer 538 offilm (e.g., approximately 400 A) is deposited at approximately 400degrees Celsius. Note that layer 538 comprises a layer of PE-oxide.

[0129]FIG. 46 illustrates an eighth step 546 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 46, a capacitor top metal (CTM) is deposited, whichincludes TiN (e.g., 250A), Al—Cu (1200 A), and TiN (e.g., 700 A) layers.Note that a layer 542 of TiN (e.g., 750 A) is illustrated above a layer540 of Al—Cu (e.g. 1.2 kA) and a layer 571 of TiN. Layer 571 is locatedabove layer 538 (i.e., PE-oxide layer).

[0130]FIG. 47 depicts a ninth step 547 of a fabrication process inaccordance with an alternative embodiment of the present invention. FIG.57 illustrates deposition of an SION BARC layer 574 (e.g., approximately320 A) and a capacitor top metal (CTM) photo patterning indicated bylayer 576. Note that layer 576 is a photoresist layer.

[0131]FIG. 48 illustrates a tenth step 548 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asindicated in FIG. 48, a capacitor top metal (CTM) etching operation canbe implemented followed by a PE-oxide deposition step (i.e., CTM surfacearea is approximately 25 um×25 um).

[0132]FIG. 49 depicts an eleventh step 549 of a fabrication process inaccordance with an alternative embodiment of the present invention. Asillustrated in FIG. 49, an SION BARC deposition layer 576 ofapproximately 320 A may be deposited followed by a Metal-5 photopatterning/etching operation. Note that the SION layer 576 may also beapproximately 300 A, depending on a desired implementation.

[0133]FIG. 50 illustrates a twelfth step 550 of a fabrication process inaccordance with an alternative embodiment of the present invention. FIG.50 depicts FSG deposition (e.g., 10 kA-20 kA) and CMP planarization forinter-metal-dielectric (IMD-5) followed by Via-5 photo patterning andetching. Layer 578 thus comprises an FSG layer. Vias (i.e., Via-5) 600,602, 604 and 606 also illustrated in FIG. 5 within FSG layer 578.

[0134]FIG. 51 depicts a thirteenth step 551 of a fabrication process inaccordance with an alternative embodiment of the present invention. FIG.51 depicts Ti/TiN/W depositions for Via-5 filling, followed by CMPisolation. Note that via-5 is filled with W (i.e., Tungsten). FIG. 52illustrates a sixteenth step 552 of a fabrication process in accordancewith an alternative embodiment of the present invention. FIG. 52indicates metal-6 (i.e., TiN/Cu—Al/TiN) depositions followed photopatterning and etching.

[0135] The embodiments and examples set forth herein are presented tobest explain the present invention and its practical application and tothereby enable those skilled in the art to make and utilize theinvention. Those skilled in the art, however, will recognize that theforegoing description and examples have been presented for the purposeof illustration and example only. Other variations and modifications ofthe present invention will be apparent to those of skill in the art, andit is the intent of the appended claims that such variations andmodifications be covered. The description as set forth is thus notintended to be exhaustive or to limit the scope of the invention. Manymodifications and variations are possible in light of the above teachingwithout departing from scope of the following claims. It is contemplatedthat the use of the present invention can involve components havingdifferent characteristics. It is intended that the scope of the presentinvention be defined by the claims appended hereto, giving fullcognizance to equivalents in all respects.

What is claimed is:
 1. A method for fabricating an MIM capacitor on asubstrate, said method comprising the steps of: dedicating a region ofsaid substrate for use as an electrode area of said MIM capacitor; andincreasing said electrode area of said MIM capacitor by at least onespacer formed on an associated planar metal surface, wherein said planarmetal surface is formed upon said substrate, such that an increase in again factor of said electrode area is dependent upon an associatedspacer height and particular islands or vias thereof.
 2. The method ofclaim 1 further comprising the step of: forming at least one sacrificialisland upon a metal surface formed upon said substrate.
 3. The method ofclaim 1 wherein said at least one spacer comprises a conducting materialformed upon said substrate.
 4. The method of claim 3 wherein said atleast one sacrificial island comprises an oxide island.
 5. The method ofclaim 3 wherein said conducting material comprises TiN.
 6. The method ofclaim 3 wherein said conducting material comprises TaN.
 7. The method ofclaim 3 further comprises the step of: forming said at least one spacerthrough deposition and etching.
 8. The method of claim 3 wherein said atleast one spacer provides a short to said metal surface formed belowsaid at least one spacer.
 9. The method of claim 3 further comprisingthe step of: removing said at least sacrificial island, such said metalsurface with said at least one space formed there above comprises aroughened electrode for use in said MIM capacitor formed upon saidsubstrate.
 10. The method of claim 8 wherein said MIM capacitorcomprises a low-temperature MIM capacitor.
 11. A method for fabricatingan MIM capacitor on a substrate, said method comprising the steps of:dedicating a region of said substrate for use as an electrode area ofsaid MIM capacitor; forming at least one oxide island upon a metalsurface formed upon said substrate, wherein at least one spacer formedabout said at least one oxide island comprises a conducting material;adapting said at least one spacer for use as a short to said metalsurface formed below said at least one spacer; removing said at leastone oxide island, such said metal surface with said at least one spaceformed there above comprises a roughened electrode for use in said MIMcapacitor formed upon said substrate; forming said MIM capacitor uponsaid substrate, wherein said MIM capacitor comprises a low-temperatureMIM capacitor; and increasing said electrode area of said MIM capacitorutilizing said at least one spacer, such that an increase in a gainfactor of said electrode area is dependent upon an associated spacerheight and particular oxide islands or vias thereof.
 12. The method ofclaim 11 further comprising the step of: forming a metal layer upon saidsubstrate; forming at least one oxide via upon said metal layer.
 13. Themethod of claim 12 further comprising the step of: filling said at leastone oxide via with a protection material.
 14. The method of claim 13wherein said protection material comprises a photo-resist.
 15. Themethod of claim 13 wherein said protection material comprises an organicmaterial.
 16. The method of claim 13 wherein the step of filling said atleast one oxide via with a protection material, further comprises thestep of: filling said at least one oxide via with a protection materialby spin coating and removal thereof until at least one oxide surface isexposed.
 17. The method of claim 16 further comprising the step of:performing an anisotropic oxide etch to form at least one oxide spacerabout said at least one oxide via.
 18. The method of claim 17 furthercomprising the steps of: cleaning said substrate and structures formedthereupon; and coating said at least one oxide space with a thinconducting material to form a roughened electrode surface thereof. 19.The method of claim 18 further comprising the step of: forming said MIMcapacitor upon said substrate wherein said MIM capacitor includes saidroughened electrode surface for use as said electrode area.
 20. A methodfor fabricating an MIM capacitor on a substrate, said method comprisingthe steps of: forming a bottom metal electrode on said substrate;forming a sacrificial layer upon said bottom metal electrode; patterningsaid sacrificial layer into an island structure to form an islandsacrificial structure; forming a first diffusion layer on said islandsacrificial structure; forming at least one space by said firstdiffusion layer; removing said island sacrificial structure; forming asecond diffusion layer on said at least one spacer; forming a dielectriclayer; and forming a top metal electrode thereon.
 21. The method ofclaim 20 wherein said bottom metal electrode is Al—Cu.
 22. The method ofclaim 20 further comprising the step of: forming an adhesion layerbetween said bottom metal electrode and said substrate.
 23. The methodof claim 22 wherein said adhesion layer comprises TiN.
 24. The method ofclaim 20 wherein said sacrificial layer comprises oxide.
 25. The methodof claim 20 wherein said diffusion first layer comprises TiN.
 26. Themethod of claim 20 wherein said at least one spacer is formed as aresult of an etch back step.
 27. The method of claim 20 wherein saidsecond diffusion layer comprises TiN.
 28. The method of claim 20 whereinsaid top metal electrode comprises Al—Cu.
 29. The method of claim 28further comprising the step of: forming a third diffusion layer on saidtop metal electrode.
 30. The method of claim 29 wherein said thirddiffusion layer comprises TiN.
 31. The method of claim 20 furthercomprising the step of: forming a photoresist above said third diffusionlayer; performing a capacitor top metal (CTM) etching operation;depositing an SiON BARC deposition layer followed thereafter by ametal-5 photo patterning and etching operation; depositing an FSG layerthereon; performing a chemical mechanical polishing operation;thereafter performing a photo patterning and etching operation;depositing Ti, TiN and W for Via-5 filling; thereafter performing achemical mechanical polishing isolation operation; and forming a metal-6layer based on a TiN/Cu—Al/Tin deposition followed thereafter by photopatterning and etching.
 32. An MIM capacitor formed on a substrate, saidMIM capacitor comprising: a region of said substrate dedicated for useas an electrode area of said MIM capacitor; and wherein said electrodearea of said MIM capacitor may be increased utilizing at least onespacer formed on an associated planar metal surface, wherein said planarmetal surface is formed upon said substrate, such that an increase in again factor of said electrode area is dependent upon an associatedspacer height and particular islands or vias thereof.
 33. The MIMcapacitor of claim 32 further comprising at least one sacrificial islandformed upon a metal surface on said substrate.
 34. The MIM capacitor ofclaim 32 wherein said at least one spacer comprises a conductingmaterial formed upon said substrate.
 35. The MIM capacitor of claim 34wherein said at least one sacrificial island comprises an oxide island.36. The MIM capacitor of claim 34 wherein said conducting materialcomprises TiN.
 37. The MIM capacitor of claim 34 wherein said conductingmaterial comprises TaN.
 38. The MIM capacitor of claim 34 wherein saidat least one spacer is formed through deposition and etching.
 39. TheMIM capacitor of claim 34 wherein said at least one spacer provides ashort to said metal surface formed below said at least one spacer. 40.The MIM capacitor of claim 34 wherein said at least sacrificial islandis removed, such said metal surface with said at least one space formedthere above comprises a roughened electrode for use in said MIMcapacitor formed upon said substrate.
 41. The MIM capacitor of claim 39wherein said MIM capacitor comprises a low-temperature MIM capacitor.42. A MIM capacitor for fabricating an MIM capacitor on a substrate,said MIM capacitor comprising: a region of said substrate dedicated foruse as an electrode area of said MIM capacitor; at least one oxideisland formed upon a metal surface formed upon said substrate, whereinat least one spacer formed about said at least one oxide islandcomprises a conducting material; said at least one spacer adapted foruse as a short to said metal surface formed below said at least onespacer; wherein said at least one oxide island is removed, such saidmetal surface with said at least one space formed there above comprisesa roughened electrode for use in said MIM capacitor formed upon saidsubstrate; wherein said MIM capacitor formed upon said substrate,wherein said MIM capacitor comprises a low-temperature MIM capacitor;and wherein said at least one spacer utilized to increase said electrodearea of said MIM capacitor, such that an increase in a gain factor ofsaid electrode area is dependent upon an associated spacer height andparticular oxide islands or vias thereof.
 43. The MIM capacitor of claim42 further comprising: a metal layer formed upon said substrate; atleast one oxide via formed upon said metal layer.
 44. The MIM capacitorof claim 43 further comprising the step of: a protection material thatfills said at least one oxide via.
 45. The MIM capacitor of claim 44wherein said protection material comprises a photoresist.
 46. The MIMcapacitor of claim 44 wherein said protection material comprises anorganic material.
 47. The MIM capacitor of claim 44 wherein said atleast one oxide via is filled with a protection material by spin coatingand removal thereof until at least one oxide surface is exposed.
 48. TheMIM capacitor of claim 47 wherein at least one oxide spacer is formedaround said at least one oxide via by performing an anisotropic oxideetch.
 49. The MIM capacitor of claim 48 wherein said substrate andstructures formed thereupon are cleaned and wherein said at least oneoxide spacer is coated with a thin conducting material to form aroughened electrode surface thereof.
 50. The MIM capacitor of claim 49wherein said MIM capacitor is formed upon said substrate, such that saidMIM capacitor includes said roughened electrode surface for use as saidelectrode area.
 51. A MIM capacitor for fabricating an MIM capacitor ona substrate, said method comprising the steps of: a bottom metalelectrode formed on said substrate; a sacrificial layer formed upon saidbottom metal electrode; said sacrificial layer patterned into an islandstructure to form an island sacrificial structure; a first diffusionlayer formed on said island sacrificial structure; at least one spacerformed by said first diffusion layer, wherein said island sacrificialstructure is removed thereafter; a second diffusion layer formed on saidat least one spacer; a dielectric layer formed thereon; and a top metalelectrode thereon.
 52. The MIM capacitor of claim 51 wherein said bottommetal electrode is Al—Cu.
 53. The MIM capacitor of claim 51 wherein anadhesion layer is formed between said bottom metal electrode and saidsubstrate.
 54. The MIM capacitor of claim 53 wherein said adhesion layercomprises TiN.
 55. The MIM capacitor of claim 51 wherein saidsacrificial layer comprises oxide.
 56. The MIM capacitor of claim 51wherein said diffusion first layer comprises TiN.
 57. The MIM capacitorof claim 51 wherein said at least one spacer is formed as a result of anetch back step.
 58. The MIM capacitor of claim 51 wherein said seconddiffusion layer comprises TiN.
 59. The MIM capacitor of claim 51 whereinsaid top metal electrode comprises Al—Cu.
 60. The MIM capacitor of claim59 wherein a third diffusion layer is formed on said top metalelectrode.
 61. The MIM capacitor of claim 60 wherein said thirddiffusion layer comprises TiN.
 62. The MIM capacitor of claim 61 furthercomprising: a photoresist formed above said third diffusion layer; anSiON BARC deposition layer; an FSG layer deposited thereon; Ti, TiN andW filled within one or more Via-5 structures; and a metal-6 layer formedthereon based on a TiN/Cu—Al/Tin deposition operation.